1. Field of the Invention
The present invention relates to a two-port SRAM (Static Random Access Memory), and more particularly, to an improved high speed two-port SRAM having a write-through function wherein a sense amplifier and a write-through function are combined.
2. Description of the Background Art
As shown in FIG. 1, a conventional two-port SRAM includes: first and second inverters IN1, IN2 respectively inverting a data signal DATA and a data bar signal DATAB outputted from a memory cell (not shown); a third inverter IN3 inverting an output signal of the first inverter IN1 and outputting the thusly inverted signal to an input terminal of the first inverter IN1; a fourth inverter IN4 inverting an output signal of the second inverter IN2 and outputting the thusly inverted signal to an input terminal of the fourth inverter IN4; a NAND gate ND1 NANDing the respective output signals of the first inverter IN1 and the second inverter IN2; a first PMOS transistor PM1 to the gate of which is applied an output signal of the NAND gate ND1, to the source of which is applied supply voltage Vcc, and the drain of which is connected to an input terminal of the first inverter IN1; a second PMOS transistor PM2 a gate of which is connected to that of the first PMOS transistor PM1, to the source of which is applied the supply voltage Vcc, and a drain of which is connected to an input terminal of the second inverter IN2; and a fifth inverter IN5 inverting an output signal of the second inverter IN2 and externally outputting the thusly inverted signal. Here, reference characters A, B, C designate nodes coupled to respective elements.
With reference to FIGS. 1 and 2A-2E, the operation of the thusly constituted conventional two-port SRAM will now be described.
As shown in FIG. 2A with regard to region 1 of FIGS. 2A-2E, when the data signal DATA and data bar signal DATAB outputted from a memory cell (not shown) are at a high level, if the data signal DATA is transited from high to low level, the signal at a first node A in FIG. 2B is transited to a high level in accordance with the output of the first inverter IN1.
At this time, the data bar signal DATAB remains at a high level, so that a second node B is maintained at a low level as shown in FIG. 2C. Accordingly, the signal at the third node C remains at a high level as shown in FIG. 2D in accordance with the output of the NAND gate ND1, so that the first and second PMOS transistors P1, P2 are maintained in an off state, respectively.
The fifth inverter IN5 which receives the signal of the second node B outputs an output signal OUTPUT at a low level.
As shown in FIG. 2A with regard to region 2 of FIGS. 2A-2E, the data signal DATA outputted from the memory cell (not shown) is not converted to a high level because the driving capability of the third inverter IN3 for carrying out a latching function is large. Instead, the data signal DATA inverted by the first inverter IN1 is maintained at a low level. Meanwhile, the data bar signal DATAB applied to the second inverter IN2 is transited to a low level because the driving capability of the memory cell (not shown) is larger than that of the fourth inverter IN4.
As shown in FIG. 2C, the signal at the second node B is transited to a high level in accordance with the output of the second inverter IN2, and the output of the NAND gate ND1 which receives the signal at the second node B and the high level signal at the first node A is transited to a low level. That is, the signal at the third node C in FIG. 2D is transited to a low level.
The first and second MOS transistor P1, P2 are turned on by the low level third node C signal applied to their gates, so that the data signal DATA and the data bar signal applied to the first inverter IN1 and the third inverter IN3 are transited to a high level, respectively. Also, the signal at first node A and the signal at second node B are transited to a low level, respectively, as shown in FIGS. 2B and 2C.
Then, as shown in FIG. 2E, the output signal OUTPUT is outputted at a high level by the fifth inverter IN5.
However, the conventional two-port SRAM allows the data signal DATA outputted from the memory cell (not shown) to be outputted via the first inverter IN1, and experiences an aggravated amplification capability, thereby lowering the speed. Moreover, a sense amplifier does not exist in the read path and the signal is sensed by inverters, so that although a write-through operation is carried out, a read access time becomes significantly delayed. Further, in order to increase the read access time, the memory cell driving capability should be large enough and accordingly the memory cell becomes increased in size.